What work have you done on full chip Clock and Power
distribution? What process technology and budgets were used?
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Give the various techniques you know to minimize power consumption?
Implement F= not (AB+CD) using CMOS gates?
How about voltage source?
What is the depletion region?
What is validation?
What are the different measures that are required to achieve the design for better yield?
Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
what is body effect?
Have you studied buses? What types?
Are you familiar with the term MESI?
What types of high speed CMOS circuits have you designed?
What is latchup? Explain the methods used to prevent it?