For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)


No Answer is Posted For this Question
Be the First to Post Answer

Post New Answer

More VLSI Interview Questions

How does a pn junction works?

2 Answers   Wipro,


What happens if we increase the number of contacts or via from one metal layer to the next?

1 Answers   Infosys,


Tell me the parameters as many as possible you know that used to character an amplifier?

1 Answers  


Different ways of implementing a comparator?

1 Answers   Intel,


Implement a function with both ratioes and domino logic and merits and demerits of each logic?

0 Answers   Intel,


Are you familiar with VHDL and/or Verilog?

1 Answers   Intel,


Why does the present vlsi circuits use mosfets instead of bjts?

0 Answers  


What products have you designed which have entered high volume production?

1 Answers   Intel,


In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

0 Answers   Infosys,


What are the total number of lines written by you in C/C++? What compiler was used?

1 Answers   Intel, Zensar,


Explain the difference between write through and write back cache.

2 Answers   Intel,


What is the difference between nmos and pmos technologies?

0 Answers  


Categories