Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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What are the two types of noise of MOSFET, how to eliminate them?(Thermal and Flicker).

4 Answers   Analog Devices,

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Explain the various Capacitances associated with a transistor and which one of them is the most prominent?

2 Answers   Intel,

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What's the price in 1K quantity?

0 Answers   Wipro,

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what is multiplexer?

0 Answers  

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What are set up time & hold time constraints? What do they signify?

3 Answers  

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You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

4 Answers   Intel,

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What are the Advantages and disadvantages of Mealy and Moore?

0 Answers   Intel,

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

3 Answers   Intel,

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What happens if we use an Inverter instead of the Differential Sense Amplifier?

0 Answers   Infosys,

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Differences between D-Latch and D flip-flop?

17 Answers   AIT, Intel, Sibridge Technologies,

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What are the different types of skews used in vlsi?

1 Answers  

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