Suppose you have a combinational circuit between two
registers driven by a clock. What will you do if the delay
of the combinational circuit is greater than your clock
signal? (You can't resize the combinational circuit
transistors)
Answer Posted / guest
Ideally, clock period will be increased (reducing maximum
operation frequency)
Is This Answer Correct ? | 3 Yes | 3 No |
Post New Answer View All Answers
Are you familiar with the term MESI?
Explain what is Verilog?
How does Vbe and Ic change with temperature?
Mention what are three regions of operation of mosfet and how are they used?
How to improve these parameters? (Cascode topology, use long channel transistors)
Explain what is the depletion region?
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
What are the steps involved in designing an optimal pad ring?
What products have you designed which have entered high volume production?
Implement a function with both ratioed and domino logic and merits and demerits of each logic?
What is the ideal input and output resistance of a current source?
For CMOS logic, give the various techniques you know to minimize power consumption
What are the main issues associated with multiprocessor caches and how might you solve them?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
Explain how binary number can give a signal or convert into a digital signal?