Explain about stuck at fault models, scan design, BIST and
IDDQ testing?
- 3 Answers
- 12093 Views
- Intel, I also Faced
- E-Mail Answers
Answers were Sorted based on User's Feedback
Answer / navya
IDDQ testing:usually performed at the beginning of test cycle.The test checks for leakage current to know if it is in normal range or abnormal range.If abnormal die fails,it is rejected and no further tests are performed.Iddq testing can detect clusters of gate oxide shorts(GOS) where gate voltage has no control over drain current and they tend to increase leakage levels.
BIST(built in self test): used to meet requirements such as high reliability and low repair cycle times.Bist reduces need for external testing(ATE).But the disadvantage is additional silicon area needed to implement BIST circuitry.
Scan design:test methodology built into digital chips
All flipflop are provided with alternate i/p for data as well as a separate clk i/p for scan testing.F/f connected together in scan chains.Testing is done by entering a special test mode called "scan mode" where test vectors is i/p to each scan chain and the bits clkd through all f/f's in the chain with resulting o/p chkd for errors.
Stuck at fault models:
stuck-on fault:always conducts Ids with an applied Vds,gate has no control over the operation
stuck off faults:current never flows regardless of Vgs or Vds.
| Is This Answer Correct ? | 13 Yes | 1 No |
Answer / seetharamukg
IDDQ testing is used for testing the library cells. Meaning
if any faults are there in our design we are going for DFT.
If any faults are there in the library itself we are doing
IDDQ testing.
| Is This Answer Correct ? | 3 Yes | 9 No |
Answer / shashank parashar
BIST is a biult in self test,in which we are going to test
our circuit in chip only.
Dft is a design for test.
IDDQ testing is used for testing the library cells.
| Is This Answer Correct ? | 3 Yes | 9 No |
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
Different ways of implementing a comparator?
In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
If not into production, how far did you follow the design and why did not you see it into production?
Give the expression for calculating Delay in CMOS circuit?
Differences between netlist of HSPICE and Spectre?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What is the difference between nmos and pmos technologies?
Tell me the parameters as many as possible you know that used to character an amplifier?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
Differences between Array and Booth Multipliers?
86 Family 
