If the current thru the poly is 20nA and the contact can
take a max current of 10nA how would u overcome the problem?
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
What are the steps required to solve setup and hold violations in vlsi?
What is look up table in vlsi?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What is the depletion region?
Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
How do you detect a sequence of "1101" arriving serially from a signal line?
What is latchup? Explain the methods used to prevent it?
what is charge sharing?
What is Body Effect?
0 Answers CG CoreEL, Cisco, TA,
What is the ideal input and output resistance of a current source?