Answer / kamal

Place two contacts on poly.

Implement a function with both ratioes and domino logic and merits and demerits of each logic?

0 Answers   Intel,

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Explain Cross section of an NMOS transistor?

0 Answers   Intel,

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Insights of a 2 input NAND gate. Explain the working?

1 Answers   Intel,

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What happens to delay if you increase load capacitance?

1 Answers   Google,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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What types of CMOS memories have you designed? What were their size? Speed?

0 Answers   e-tec, Intel,

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Differences between IRSIM and SPICE?

0 Answers   Intel,

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What are the steps required to solve setup and hold violations in vlsi?

0 Answers  

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Draw a CMOS Inverter. Explain its transfer characteristics

0 Answers   Infosys,

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What are the different design techniques required to create a layout for digital circuits?

0 Answers  

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Cross section of a PMOS transistor?

0 Answers   Intel,

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Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

1 Answers   IIT, Intel,

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