Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...


Implement F = AB+C using CMOS gates?

Answers were Sorted based on User's Feedback



Implement F = AB+C using CMOS gates?..

Answer / nehru

cmos design combination of both pmos and nmos.pmos is pull
up network.nmos pull down network.A TRANISTOR IS CONNECTED
SERIES WITH B TRANSISTOR.THE SERIES COMBINATION OF BOTH
A AND B TRANSISTOR CONNECTED PARALLEL WITH C TRANSISTOR(IN
PULL DOWN CKT).THEN APPLY DUALITY PROPERTY TO PMOS.THEN
FINAL OUTPUT IS COMPLEMENTED BY CMOS INVERTER.THIS FUNCTION
IMPLEMENTED IN DIFFERENT LOGICS
1.CMOS LOGIC
2.C2 MOS LOGIC
3.NP LOGIC
4.DYNAMIC LOGIC
5.PASS TRANSISTOR LOGIC
6.DOMINO LOGIC
7.DIFFERENTIAL CASCADE VOLTAGE SWITCH LOGIC
8.PSUEDO NMOS LOGIC

Is This Answer Correct ?    11 Yes 11 No

Implement F = AB+C using CMOS gates?..

Answer / radhika

CMOS gate consists of both NMOS and PMOS.
Two NMOS ,a and b are connected in series with each other and their series combination is in parallel with c named nmos.For PMOS ,a and b are connected in parallel with each other and this parallel combination is in series with c named pmos.Output is taken from PMOS and NMOS junction.

Is This Answer Correct ?    1 Yes 3 No

Post New Answer

More VLSI Interview Questions

Explain ASIC Design Flow?

2 Answers   Intel, JK Associates, Mind Tree,


Explain about stuck at fault models, scan design, BIST and IDDQ testing?

3 Answers   Intel,


Advantages and disadvantages of Mealy and Moore?

2 Answers   Intel,


Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

0 Answers   Intel,


If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

0 Answers   Intel,


Explain various adders and difference between them?

0 Answers   Intel,


Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,


Explain why is the number of gate inputs to cmos gates usually limited to four?

0 Answers  


Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)

6 Answers  


6-T XOR gate?

0 Answers   Intel,


Mention what are the two types of procedural blocks in Verilog?

0 Answers  


What is clock feed through?

2 Answers   Intel,


Categories