What is the function of tie-high and tie-low cells?
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Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?
What happens when the gate oxide is very thin?
Id vs. Vds Characteristics of NMOS and PMOS transistors?
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Draw a CMOS Inverter. Explain its transfer characteristics
What does it mean “the channel is pinched off”?
Who provides the DRC rules?
For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What is Fermi level?
How can you construct both PMOS and NMOS on a single substrate?
Give various factors on which threshold voltage depends.