Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...


What is the function of tie-high and tie-low cells?


No Answer is Posted For this Question
Be the First to Post Answer

Post New Answer

More VLSI Interview Questions

Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

1 Answers   Intel,


What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?

4 Answers   Intel,


What happens when the gate oxide is very thin?

3 Answers   Intel,


Id vs. Vds Characteristics of NMOS and PMOS transistors?

1 Answers   Brillient, Intel, ISRO,


Draw a CMOS Inverter. Explain its transfer characteristics

0 Answers   Infosys,


What does it mean “the channel is pinched off”?

0 Answers  


Who provides the DRC rules?

5 Answers   Intel,


For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

3 Answers   Intel,


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45&#61549;m wide metal wire with sheet resistance R = 0.065 &#61527;/ and Cpermicron= 0.25 fF/&#61549;m. The resistance and capacitance of the unit NMOS are 6.5k&#61527; and 2.5fF. Use a 3 segment &#61552;-model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  


What is Fermi level?

5 Answers  


How can you construct both PMOS and NMOS on a single substrate?

0 Answers   IBM, Intel,


Give various factors on which threshold voltage depends.

0 Answers  


Categories