What is the function of tie-high and tie-low cells?
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What is threshold voltage?
Explain what is scr (silicon controlled rectifier)?
Explain the Charge Sharing problem while sampling data from a Bus?
Explain how logical gates are controlled by Boolean logic?
What was your role in the silicon evaluation or product ramp? What tools did you use?
Explain what is the depletion region?
What is interrupt latency?
Explain the Working of a 2-stage OPAMP?
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
What is the depletion region?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What is the difference between = and == in C?