Answer Posted / rakesh

ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;

entity DFlip_Flop is
port(
D : in STD_LOGIC;
CLK : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC
);
end DFlip_Flop;

Architecture of DFlip_Flop is

begin

---ANother way of writing code for creating D_Flip_Flop in VHDL

process(Clk, Rst)
begin
if (Rst ='1') then
Q <= '0';
elsif(clk='1' and clk'event) then
Q <= D;
end if;
end process;

end ;

Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

1117

---

Explain Cross section of an NMOS transistor?

1048

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Explain why present VLSI circuits use MOSFETs instead of BJTs?

1159

---

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2900

---

Explain how MOSFET works?

3249

---

How can you model a SRAM at RTL Level?

5745

---

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2193

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1141

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4258

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How do you size NMOS and PMOS transistors to increase the threshold voltage?

3039

---

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

1467

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4092

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In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

4136

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1197

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what is the use of defpararm?

1155

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