What is latchup? Explain the methods used to prevent it?

2 Answers   Intel,

---

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

---

What is the difference between fifo and the memory?

6 Answers   DewSoft, Intel, Pentagon Rugged Systems,

---

What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

0 Answers   Infosys,

---

what is a sequential circuit?

0 Answers  

---

Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

---

Cross section of a PMOS transistor?

0 Answers   Intel,

---

What is Noise Margin? Explain the procedure to determine Noise Margin?

4 Answers   Amkor, Cisco, Infosys, Intel,

---

What is SPICE?

4 Answers   Intel,

---

Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

---

For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

0 Answers   Infosys,

---

What is the critical path in a SRAM?

0 Answers  

---