What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

0 Answers   Intel,

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Are you familiar with VHDL and/or Verilog?

17 Answers   Intel,

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How to find the read failiure probablity in SRAM?

2 Answers  

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While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?

1 Answers   Intel,

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If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

0 Answers   Intel,

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Give the cross-sectional diagram of the cmos.

0 Answers  

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How do you size NMOS and PMOS transistors to increase the threshold voltage?

0 Answers   Infosys,

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What are the different limitations in increasing the power supply to reduce delay?

2 Answers  

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Mention what are the two types of procedural blocks in Verilog?

0 Answers  

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what is Early effects and their physical origin.

1 Answers  

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Explain how binary number can give a signal or convert into a digital signal?

0 Answers  

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What happens if we increase the number of contacts or via from one metal layer to the next?

1 Answers   Infosys,

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