What is the depletion region?

1 Answers  

---

What is Body Effect?

0 Answers   CG CoreEL, Cisco, TA,

---

Draw the stick diagram of a NOR gate. Optimize it

0 Answers   Infosys,

---

What happens if we delay the enabling of Clock signal?

0 Answers  

---

Write a pseudo code for sorting the numbers in an array?

2 Answers   Intel,

---

---

What is Fowler-Nordheim Tunneling?

2 Answers   Intel,

---

What types of high speed CMOS circuits have you designed?

2 Answers   Infosys, Intel,

---

Have you studied buses? What types?

1 Answers   Intel,

---

Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

---

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

---

While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?

1 Answers   Intel,

---

Explain how logical gates are controlled by Boolean logic?

0 Answers  

---