Answer Posted / harvir

ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;

entity gh_DFF is
port(
D : in STD_LOGIC;
CLK : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC
);
end gh_DFF;

architecture a of gh_DFF is
begin

process(CLK,rst)
begin
if (rst = '1') then
Q <= '0';
elsif (rising_edge(CLK)) then
Q <= D;
end if;
end process;

end a;

What is the difference between cmos and bipolar technologies?

1087

---

Explain the working of Insights of an inverter ?

1175

---

Mention what are the two types of procedural blocks in Verilog?

1219

---

Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

1311

---

What is the function of tie-high and tie-low cells?

1032

---

Are you familiar with the term snooping?

3432

---

Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

1591

---

You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

2627

---

Explain the Charge Sharing problem while sampling data from a Bus?

4659

---

Tell me how MOSFET works.

2370

---

What types of high speed CMOS circuits have you designed?

2515

---

Working of a 2-stage OPAMP?

3120

---

Explain the Working of a 2-stage OPAMP?

1147

---

Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

1242

---

Explain how binary number can give a signal or convert into a digital signal?

1070

---