Answer Posted / balaji

library ieee;
use ieee.std_logic_1164.all;

entity d_ff is
port(d,clk:in std_logic;
q,q'bar:out std_logic);
end d_ff;

architecture a_d_ff of d_ff is
begin
process(clk)
begin
if rising_edge(clk) then
q<=d;
q'bar<=not d;
end if;
end process;
end a_d_ff;

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