Answer Posted / sada

latch is level sensitive but not flip flop

Draw a CMOS Inverter. Explain its transfer characteristics

1231

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why is the number of gate inputs to CMOS gates usually limited to four?

1398

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Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

1123

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What are the various regions of operation of mosfet? How are those regions used?

1183

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing transistor width.

1344

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Mention what are the different gates where Boolean logic are applicable?

1188

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Explain the operation of a 6T-SRAM cell?

4570

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3925

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Differences between IRSIM and SPICE?

5480

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Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

1409

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If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

1182

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What is the ideal input and output resistance of a current source?

3062

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Explain the working of 4-bit Up/down Counter?

4488

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6-T XOR gate?

4296

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For CMOS logic, give the various techniques you know to minimize power consumption

1455

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