What is the function of tie-high and tie-low cells?

0 Answers  

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In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

0 Answers  

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What is a D-latch? Write the VHDL Code for it?

3 Answers   Intel,

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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,

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Explain why & how a MOSFET works?

2 Answers   Infosys,

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What are the main issues associated with multiprocessor caches and how might you solve them?

1 Answers   Intel,

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How does Vbe and Ic change with temperature?

0 Answers   Qualcomm,

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What are the different classification of the timing control?

0 Answers  

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Explain depletion region.

0 Answers  

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What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

0 Answers   Infosys,

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What is validation?

2 Answers   Intel,

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Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

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