Explain ASIC Design Flow?

2 Answers   Intel, JK Associates, Mind Tree,

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Differences between DRAM and SRAM?

14 Answers   Infosys, Intel, University, Wipro,

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Mention what are the two types of procedural blocks in Verilog?

0 Answers  

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What is the mealy and moore machine's state diagram that can detect 3 consecutive heads of 3 coins ?

2 Answers  

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Differences between D-Latch and D flip-flop?

17 Answers   AIT, Intel, Sibridge Technologies,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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What is clock feed through?

2 Answers   Intel,

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What is the difference between = and == in C?

5 Answers   Intel,

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Insights of a 2 input NOR gate. Explain the working?

1 Answers   Infosys, Intel,

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WHAT IS THE DIFFERENCE BETWEEN TESTING AND VERIFICATION OF VLSI CIRCUIT?

5 Answers   Intel, Wipro,

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What are the different limitations in increasing the power supply to reduce delay?

2 Answers  

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What are the different design constraints occur in the synthesis phase?

0 Answers  

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