Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

---

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

0 Answers   Infosys,

---

Implement F= not (AB+CD) using CMOS gates?

1 Answers   Intel,

---

What happens if we use an Inverter instead of the Differential Sense Amplifier?

0 Answers  

---

Factors affecting Power Consumption on a chip?

7 Answers   Intel,

---

What are the different types of skews used in vlsi?

1 Answers  

---

Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

---

For CMOS logic, give the various techniques you know to minimize power consumption

0 Answers   Infosys,

---

what is Early effects and their physical origin.

1 Answers  

---

Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

---

What are set up time & hold time constraints? What do they signify?

3 Answers  

---

What is validation?

2 Answers   Intel,

---