A circuit has 1 input X and 2 outputs A and B. If X = HIGH
for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B =
1. Draw a state diagram for this Spec?
- 3 Answers
- 8892 Views
- Intel, I also Faced
- E-Mail Answers
Answers were Sorted based on User's Feedback
Answer / user
PS X NS A B
S0 0 S1 0 0
S0 1 S2 0 0
S1 0 S3 0 0
S1 1 S2 0 0
S2 0 S1 0 0
S2 1 S4 0 0
S3 0 S5 0 0
S3 1 S2 0 0
S4 0 S1 0 0
S4 1 S6 0 0
S5 0 S5 0 1
S5 1 S2 0 0
S6 0 S1 0 0
S6 1 S6 1 0
| Is This Answer Correct ? | 5 Yes | 1 No |
Answer / amit malik
Output Swept
------------------------
PS X NS A B
S0 0 S1 0 0
S0 1 S2 0 0
S1 0 S3 0 0
S1 1 S2 0 0
S2 0 S1 0 0
S2 1 S4 0 0
S3 0 S5 0 0
S3 1 S2 0 0
S4 0 S1 0 0
S4 1 S6 0 0
S5 0 S1 0 1
S5 1 S2 0 0
S6 0 S1 0 0
S6 1 S2 1 0
| Is This Answer Correct ? | 4 Yes | 4 No |
Answer / techie
PS X NS A B
S0 0 S1 0 0
S0 1 S2 0 0
S1 0 S3 0 0
S1 1 S2 0 0
S2 0 S1 0 0
S2 1 S4 0 0
S3 0 S5 0 0
S3 1 S2 0 0
S4 0 S1 0 0
S4 1 S6 0 0
S5 0 S0 0 1
S5 1 S2 0 0
S6 0 S1 0 0
S6 1 S0 1 0
This would be for non overlapping sequence. The above post correctly captrued overlapping sequence.
| Is This Answer Correct ? | 1 Yes | 1 No |
Have you studied buses? What types?
Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
What are set up time & hold time constraints? What do they signify?
Explain why & how a MOSFET works?
Implement F= not (AB+CD) using CMOS gates?
What are the Factors affecting Power Consumption on a chip?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
Explain the Various steps in Synthesis?
Draw the Layout of an Inverter?
What is the difference between = and == in C?
In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
86 Family 
