Id vs. Vds Characteristics of NMOS and PMOS transistors?
What are the various regions of operation of mosfet? How are those regions used?
What is clock feed through?
What happens to delay if you increase load capacitance?
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
What are the changes that are provided to meet design power targets?
What are the steps involved in preventing the metastability?
Explain sizing of the inverter?
verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0.
2 Answers Cosmic Circuits, HP,
Explain the working of 4-bit Up/down Counter?
Explain why is the number of gate inputs to cmos gates usually limited to four?
what is the difference between the testing and verification?
Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
0 Answers Intel, Sun Microsystems,