Answer / guest

232133

Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

---

Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)

6 Answers  

---

Insights of a 2 input NOR gate. Explain the working?

1 Answers   Infosys, Intel,

---

Explain the working of Insights of a pass gate ?

0 Answers   Intel,

---

For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

0 Answers   Infosys,

---

---

What are the main issues associated with multiprocessor caches and how might you solve them?

0 Answers   Intel,

---

What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

0 Answers   Intel,

---

How do you size NMOS and PMOS transistors to increase the threshold voltage?

4 Answers  

---

If the current through the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

0 Answers   Intel,

---

What is pipelining and how can we increase throughput using pipelining?

1 Answers   Intel,

---

In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

0 Answers   Infosys,

---

Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

---