Give the various techniques you know to minimize power
consumption?
Answers were Sorted based on User's Feedback
Answer / garima
1.Dynamic Frequency scaling: use of programmable dividers.
2. Good RTL coding techinques,
1.using clock gating cells during RTL phasing with
intelligent gating enabling logic.
2. using gray coding.
Do not depen entirely on sythesis inserted clock gating
3. Dynamic Voltage scaling.
4. Low power modes: application based most of the cores ex
ARM supports various modes.
5. Power Gating : SRPG.
Is This Answer Correct ? | 6 Yes | 0 No |
Answer / narayanachowdary
clock gating
multiple thresholdvoltages,
logic restructuring,....
Is This Answer Correct ? | 2 Yes | 0 No |
Answer / narendra
Hi Panchamiukhi, can you please elaborate on 2nd and 3rd
options? They sound interesting but didnt understand. Thanks
Is This Answer Correct ? | 0 Yes | 0 No |
Answer / jaya suriya.i
1.reduce the vdd.its
2.using short channel devices(its very complicated).
3.reduce the load capacitance of cmos..
Is This Answer Correct ? | 0 Yes | 0 No |
Answer / panchamukhi.ellur
Various techniques are available to minimize the power
consumption such as
1)Multiple vdd technique ,depnding on application and power
required for that particular module use specific power
supply(vdd).
2)Using multiple thickness of THINOXIDE
3)To avoid short ckt current stack tecniques
Is This Answer Correct ? | 0 Yes | 4 No |
What happens if we delay the enabling of Clock signal?
How to find the read failiure probablity in SRAM?
Draw a CMOS Inverter. Explain its transfer characteristics
Cross section of a PMOS transistor?
How to improve these parameters? (Cascode topology, use long channel transistors)
Explain how Verilog is different to normal programming language?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B = 1. Draw a state diagram for this Spec?
what is SCR (Silicon Controlled Rectifier)?
What are the main issues associated with multiprocessor caches and how might you solve them?
How about voltage source?
If the substrate doping concentration increase, or temperature increases, how will Vt change? it increase or decrease?