Answer / banibrata

1/2 C V^2.f

Answer / arpan

P=CL * Vdd^2 * f
CL= Load capacitance
VDD = Supply Voltage
f= Switching frequency

During high to low transition the load
capacitance is discharged and during low to high transition
the load capacitance is charged.

Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

0 Answers   Infosys,

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What are the limitations in increasing the power supply to reduce delay?

2 Answers   Infosys,

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In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

3 Answers   IBM, Intel, nvidia,

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0 Answers   Intel,

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0 Answers   Intel,

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0 Answers   Qualcomm,

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1 Answers  

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Cross section of an NMOS transistor?

3 Answers   Intel,

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0 Answers   Intel,

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0 Answers   Infosys,

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Explain Clock Skew?

6 Answers   Intel, nvidia,

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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

0 Answers   Infosys,

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