Answer / salla nagaraju

When sampling data from a bus using CMOS transmission gates or multiplexers, charge sharing can occur, leading to incorrect logic levels at the output.

What?s the difference between Testing & Verification?

6 Answers   Infosys,

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What are the Advantages and disadvantages of Mealy and Moore?

0 Answers   Intel,

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Insights of a pass gate. Explain the working?

0 Answers   Intel,

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What is validation?

2 Answers   Intel,

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What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

0 Answers   Infosys,

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Explain about stuck at fault models, scan design, BIST and IDDQ testing?

3 Answers   Intel,

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What are the steps involved in designing an optimal pad ring?

0 Answers  

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You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

0 Answers   Intel,

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Explain the working of Insights of a pass gate ?

0 Answers   Intel,

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Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)

6 Answers  

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Draw a 6-T SRAM Cell and explain the Read and Write operations

0 Answers   Infosys,

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Explain the Various steps in Synthesis?

0 Answers   Intel,

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