Interested to Buy Any Domain ? << Click Here >> for more details...
What are the limitations in increasing the power supply to
reduce delay?
- 2 Answers
- 13523 Views
- Infosys, I also Faced
- E-Mail Answers
Answers were Sorted based on User's Feedback
Answer / arpan
increasing vdd increeases power dissipation as
switching power = c vdd**2 f
also at submicron level , increasing vdd amy lead to hgh
feild in the device....leading to its failure
| Is This Answer Correct ? | 10 Yes | 0 No |
Answer / narasimha reddy d l
power supply is directly praportional to the sub-micron
leakage current so if Vdd increases the leakage current
will increases
| Is This Answer Correct ? | 1 Yes | 2 No |
What is the difference between nmos and pmos technologies?
Write a pseudo code for sorting the numbers in an array?
How does a pn junction works?
What are the different gates where boolean logic are applicable?
Given a circuit and asked to tell the output voltages of that circuit?
1 Answers Intel, Omega Healthcare,
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
What is Noise Margin? Explain the procedure to determine Noise Margin?
Give the various techniques you know to minimize power consumption?
What happens to delay if you increase load capacitance?
What happens to delay if you increase load capacitance?
Design an 8 is to 3 encoder using 4 is to encoder?
Explain what is slack?
86 Family 
