Answer / shashank agarwal

Since delay=f*C*Vdd^2, delay increases with the increase in the load capacitance

For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

0 Answers   Intel,

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Mention what are three regions of operation of mosfet and how are they used?

0 Answers  

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Why do we use a Clock tree?

3 Answers   Intel,

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What is clock feed through?

2 Answers   Intel,

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verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0.

2 Answers   Cosmic Circuits, HP,

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If not into production, how far did you follow the design and why did not you see it into production?

1 Answers   Intel,

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What happens if we increase the number of contacts or via from one metal layer to the next?

1 Answers   Infosys,

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Implement F= not (AB+CD) using CMOS gates?

0 Answers   Intel,

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What is interrupt latency?

3 Answers  

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Are you familiar with the term MESI?

0 Answers   Intel,

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What is the depletion region?

1 Answers  

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Are you familiar with the term snooping?

0 Answers   Intel,

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