Answer / shashank agarwal

Since delay=f*C*Vdd^2, delay increases with the increase in the load capacitance

How do you detect if two 8-bit signals are same?

6 Answers  

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Id vs. Vds Characteristics of NMOS and PMOS transistors?

1 Answers   Brillient, Intel, ISRO,

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Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

0 Answers   Intel,

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What are the steps required to solve setup and hold violations in vlsi?

0 Answers  

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Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

0 Answers   Infosys,

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Cross section of a PMOS transistor?

0 Answers   Intel,

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For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

0 Answers   Intel,

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what is conductance and valence band?

1 Answers  

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Working of a 2-stage OPAMP?

0 Answers   Intel, Tata Elxsi,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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Explain the Various steps in Synthesis?

0 Answers   Intel,

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6-T XOR gate?

0 Answers   Intel,

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