Answer / madhu

if we increase power supply to reduce delay ,delay will
reduces but power dissipation will be high and to
compensate the excessive power we have to increase die size
which is impractical.

Answer / bauer

There are also Mobility Degradation and Subthreshold Conduction which directly depend on the Voltage and Temperature.

Why don?t we use just one NMOS or PMOS transistor as a transmission gate?

2 Answers   Infosys,

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What is validation?

2 Answers   Intel,

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Explain the sizing of the inverter?

1 Answers   Intel,

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What are the different ways in which antenna violation can be prevented?

0 Answers  

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What are the two types of noise of MOSFET, how to eliminate them?(Thermal and Flicker).

4 Answers   Analog Devices,

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Write a pseudo code for sorting the numbers in an array?

2 Answers   Intel,

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Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

0 Answers   Infosys,

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Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

1 Answers   IIT, Intel,

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Cross section of an NMOS transistor?

3 Answers   Intel,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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Explain Cross section of a PMOS transistor?

0 Answers   Intel,

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Why is OOPS called OOPS? (C++)

1 Answers   ARM, Intel,

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