Answer / madhu

if we increase power supply to reduce delay ,delay will
reduces but power dissipation will be high and to
compensate the excessive power we have to increase die size
which is impractical.

Answer / bauer

There are also Mobility Degradation and Subthreshold Conduction which directly depend on the Voltage and Temperature.

In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

0 Answers  

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What is SPICE?

4 Answers   Intel,

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What is the main function of metastability in vsdl?

0 Answers  

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What are the Factors affecting Power Consumption on a chip?

0 Answers   Intel,

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Why do we use a Clock tree?

3 Answers   Intel,

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How does Vbe and Ic change with temperature?

0 Answers   Qualcomm,

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What?s the critical path in a SRAM?

2 Answers   Infosys, Intel, Texas,

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If the current thru the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

1 Answers   Intel,

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Explain the sizing of the inverter?

1 Answers   Intel,

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Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

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verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0.

2 Answers   Cosmic Circuits, HP,

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Give the expression for CMOS switching power dissipation?

2 Answers   Infosys,

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