Answer / madhu

if we increase power supply to reduce delay ,delay will
reduces but power dissipation will be high and to
compensate the excessive power we have to increase die size
which is impractical.

Answer / bauer

There are also Mobility Degradation and Subthreshold Conduction which directly depend on the Voltage and Temperature.

How does a pn junction works?

2 Answers   Wipro,

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Are you familiar with the term MESI?

1 Answers   Intel,

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You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

0 Answers   Intel,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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Insights of a 4bit adder/Sub Circuit?

0 Answers   Intel,

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Explain what is Verilog?

0 Answers  

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If not into production, how far did you follow the design and why did not you see it into production?

1 Answers   Intel,

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Implement F= not (AB+CD) using CMOS gates?

1 Answers   Intel,

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what is Slack?

0 Answers  

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What is Fowler-Nordheim Tunneling?

2 Answers   Intel,

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Explain Cross section of an NMOS transistor?

0 Answers   Intel,

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Explain what is multiplexer?

0 Answers  

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