Answer / madhu

Delay increases

Answer / jaya suriya

pd=f *c* vdd^2

power dissipation get increases.....
propagation delay get increases....
so speed of the circuit get decreased...

Answer / arpan

If load capacitance is increased then time require to charge
the capacitance increases, so the rise time increases which
in turn increases the delay.

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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0 Answers   Intel,

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0 Answers   Intel,

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1 Answers   Intel,

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1 Answers  

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1 Answers   Intel,

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0 Answers   CG CoreEL, Cisco, TA,

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0 Answers   Intel,

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what is the doping?

5 Answers  

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Are you familiar with the term snooping?

0 Answers   Intel,

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