Answer / pradeep

Noise margin simply means margin for noise. it can tolerate
some amount of noise. The senders must be held at higher
standards than the receivers. For a 5V level, a voltage
above 4.5V is considered 1, and for receiver the voltage
above 3.5V is considered 1. therefore, the noise margin
4.5-3.5=1V.
it is deigned by looking at voltage transfer function.

Answer / bhau

In digital logic design the general representation of input
and output are High and low level (1's and 0's). In actual
case when the input signal transitions the output switches
to full swing before the input has reached its full swing.
The minimum signal level to get a out put High or low is
called VIH, VIL (For inversion stage Input for getting full
output low swing and input for getting full output high
swing). For the interoperability of this logic device i.e.
to use tihs output directly to feed into next stage without
level shifting the VIL > VOL, similarly VIH < VOH. In such
condition when logic swing VIL is enough to get full swing
on Output the noise margin will be VOL-VIL. Similarly NM
for signal transitioning high is VOH-VIH.

Answer / shubham sharma

"noise margine is the max. voltage that can be added to the
logic gate input which will not affect the output."
voh>vih>vil>vol

vil=0,vol=0.
vih=1,voh=1.

Answer / bhau

In digital logic design the general representation of input
and output are High and low level (1's and 0's). In actual
case when the input signal transitions the output switches
to full swing before the input has reached its full swing.
The minimum signal level to get a out put High or low is
called VIH, VIL (For inversion stage Input for getting full
output low swing and input for getting full output high
swing). For the interoperability of this logic device i.e.
to use tihs output directly to feed into next stage without
level shifting the VIL > VOL, similarly VIH < VOH. In such
condition when logic swing VIL is enough to get full swing
on Output the noise margin will be VOL-VIL. Similarly NM
for signal transitioning high is VOH-VIH.

what is a sequential circuit?

0 Answers  

---

Explain what is the depletion region?

0 Answers  

---

6-T XOR gate?

0 Answers   Intel,

---

Cross section of an NMOS transistor?

3 Answers   Intel,

---

For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

3 Answers   Intel,

---

What are the main issues associated with multiprocessor caches and how might you solve them?

1 Answers   Intel,

---

How does Resistance of the metal lines vary with increasing thickness and increasing length?

3 Answers   Infosys,

---

Differences between netlist of HSPICE and Spectre?

1 Answers   Intel,

---

What is the difference between fifo and the memory?

6 Answers   DewSoft, Intel, Pentagon Rugged Systems,

---

What is latchup? Explain the methods used to prevent it?

2 Answers   Intel,

---

What are the different gates where boolean logic are applicable?

0 Answers  

---

What is a D-latch? Write the VHDL Code for it?

3 Answers   Intel,

---