Answer / pradeep

Noise margin simply means margin for noise. it can tolerate
some amount of noise. The senders must be held at higher
standards than the receivers. For a 5V level, a voltage
above 4.5V is considered 1, and for receiver the voltage
above 3.5V is considered 1. therefore, the noise margin
4.5-3.5=1V.
it is deigned by looking at voltage transfer function.

Answer / bhau

In digital logic design the general representation of input
and output are High and low level (1's and 0's). In actual
case when the input signal transitions the output switches
to full swing before the input has reached its full swing.
The minimum signal level to get a out put High or low is
called VIH, VIL (For inversion stage Input for getting full
output low swing and input for getting full output high
swing). For the interoperability of this logic device i.e.
to use tihs output directly to feed into next stage without
level shifting the VIL > VOL, similarly VIH < VOH. In such
condition when logic swing VIL is enough to get full swing
on Output the noise margin will be VOL-VIL. Similarly NM
for signal transitioning high is VOH-VIH.

Answer / shubham sharma

"noise margine is the max. voltage that can be added to the
logic gate input which will not affect the output."
voh>vih>vil>vol

vil=0,vol=0.
vih=1,voh=1.

Answer / bhau

In digital logic design the general representation of input
and output are High and low level (1's and 0's). In actual
case when the input signal transitions the output switches
to full swing before the input has reached its full swing.
The minimum signal level to get a out put High or low is
called VIH, VIL (For inversion stage Input for getting full
output low swing and input for getting full output high
swing). For the interoperability of this logic device i.e.
to use tihs output directly to feed into next stage without
level shifting the VIL > VOL, similarly VIH < VOH. In such
condition when logic swing VIL is enough to get full swing
on Output the noise margin will be VOL-VIL. Similarly NM
for signal transitioning high is VOH-VIH.

What are the limitations in increasing the power supply to reduce delay?

2 Answers   Infosys,

---

Give the cross-sectional diagram of the cmos.

0 Answers  

---

How to improve these parameters? (Cascode topology, use long channel transistors)

0 Answers  

---

Explain how Verilog is different to normal programming language?

0 Answers  

---

While using logic design, explain the various steps that r followed to obtain the desirable design in a well defined manner?

1 Answers   Intel,

---

What is look up table in vlsi?

0 Answers  

---

Given a circuit and asked to tell the output voltages of that circuit?

1 Answers   Intel, Omega Healthcare,

---

What are the different ways in which antenna violation can be prevented?

0 Answers  

---

What are the Factors affecting Power Consumption on a chip?

0 Answers   Intel,

---

What?s the difference between Testing & Verification?

6 Answers   Infosys,

---

What is the main function of metastability in vsdl?

0 Answers  

---

For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

0 Answers   Infosys,

---