Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...


Explain the difference between write through and write back
cache.

Answers were Sorted based on User's Feedback



Explain the difference between write through and write back cache...

Answer / sudeep

This is cache write hit policy,
1. write through:- The information is written to both the
cache and the main memory upon a hit,
2. write back:- The inforamtion is written to only cache,
the main memory is updated upon a read miss.

Is This Answer Correct ?    24 Yes 1 No

Explain the difference between write through and write back cache...

Answer / achal ubbott

1. Write Through policy is relatively slower. but offers
advantage of coherence between cache and main memory.

2. Write Back is faster and frquently used. It makes use of
Dirty bit. If the data in cache is not in coherence with
one in main memory then Dirty bit is set.

Is This Answer Correct ?    12 Yes 0 No

Post New Answer

More VLSI Interview Questions

How do you size NMOS and PMOS transistors to increase the threshold voltage?

0 Answers   Infosys,


What is Cross Talk?

4 Answers   Intel,


Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

0 Answers   Infosys,


What are the different limitations in increasing the power supply to reduce delay?

2 Answers  


Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  


What?s the critical path in a SRAM?

2 Answers   Infosys, Intel, Texas,


Factors affecting Power Consumption on a chip?

7 Answers   Intel,


What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?

4 Answers   Intel,


What happens to delay if you increase load capacitance?

3 Answers   Infosys,


What are the different ways in which antenna violation can be prevented?

0 Answers  


what is the difference between the testing and verification?

1 Answers   Intel,


Write a pseudo code for sorting the numbers in an array?

2 Answers   Intel,


Categories