Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

0 Answers   Intel,

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How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?

0 Answers   Infosys,

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How do you size NMOS and PMOS transistors to increase the threshold voltage?

0 Answers   Infosys,

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Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

0 Answers   Intel, Sun Microsystems,

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What types of CMOS memories have you designed? What were their size? Speed?

0 Answers   Intel, Wipro,

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Give the expression for calculating Delay in CMOS circuit?

1 Answers   Infosys,

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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what is the doping?

5 Answers  

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How does Vbe and Ic change with temperature?

0 Answers   Qualcomm,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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Differences between DRAM and SRAM?

14 Answers   Infosys, Intel, University, Wipro,

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Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

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