Explain the operation of a 6T-SRAM cell?

0 Answers   Intel,

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Insights of an inverter. Explain the working?

1 Answers   Intel,

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Why don?t we use just one NMOS or PMOS transistor as a transmission gate?

2 Answers   Infosys,

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What is the difference between fifo and the memory?

6 Answers   DewSoft, Intel, Pentagon Rugged Systems,

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What is latchup? Explain the methods used to prevent it?

2 Answers   Intel,

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For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?

5 Answers   Intel,

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What are the limitations in increasing the power supply to reduce delay?

2 Answers   Infosys,

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How do you size NMOS and PMOS transistors to increase the threshold voltage?

0 Answers   Infosys,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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How can you model a SRAM at RTL Level?

1 Answers  

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What happens if we delay the enabling of Clock signal?

0 Answers  

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What is interrupt latency?

3 Answers  

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