Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

13 Answers   Intel,

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Explain the difference between write through and write back cache.

2 Answers   Intel,

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Implement a function with both ratioes and domino logic and merits and demerits of each logic?

0 Answers   Intel,

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What is the function of chain reordering?

0 Answers  

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Explain why & how a MOSFET works?

2 Answers   Infosys,

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What types of high speed CMOS circuits have you designed?

0 Answers   Intel,

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What are the different design constraints occur in the synthesis phase?

0 Answers  

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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Insights of a Tri-state inverter?

1 Answers   Intel,

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

0 Answers   Infosys,

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Explain Cross section of a PMOS transistor?

0 Answers   Intel,

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6-T XOR gate?

0 Answers   Intel,

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