Calculate rise delay of a 3-input NAND gate driving a
3-input NOR gate through a 6mm long and 0.45m wide metal
wire with sheet resistance R = 0.065 / and Cpermicron=
0.25 fF/m. The resistance and capacitance of the unit NMOS
are 6.5k and 2.5fF. Use a 3 segment -model for the wire.
Consider PMOS and NMOS size of reference inverter as 2 and 1
respectively. Use appropriate sizing for the NAND and NOR gate.
- 0 Answers
- 3396 Views
- I also Faced
- E-Mail Answers
No Answer is Posted For this Question
Be the First to Post Answer
What happens to delay if we include a resistance at the output of a CMOS circuit?
Explain how MOSFET works?
What are the different ways in which antenna violation can be prevented?
Differences between functions and Procedures in VHDL?
Are you familiar with the term snooping?
Draw the stick diagram of a NOR gate. Optimize it
Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
What are the ways to Optimize the Performance of a Difference Amplifier?
Are you familiar with the term MESI?
Explain the operation considering a two processor computer system with a cache for each processor.
Explain what is the depletion region?
What products have you designed which have entered high volume production?
86 Family 
