What are the limitations in increasing the power supply to reduce delay?

2 Answers   Infosys,

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What is a D-latch? Write the VHDL Code for it?

3 Answers   Intel,

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Implement a function with both ratioed and domino logic and merits and demerits of each logic?

0 Answers   Intel,

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Explain the working of 4-bit Up/down Counter?

0 Answers   Intel,

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What is interrupt latency?

3 Answers  

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Are you familiar with the term MESI?

0 Answers   Intel,

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What is threshold voltage?

0 Answers  

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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What is the mealy and moore machine's state diagram that can detect 3 consecutive heads of 3 coins ?

2 Answers  

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what is the doping?

5 Answers  

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What are the Factors affecting Power Consumption on a chip?

0 Answers   Intel,

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How does Vbe and Ic change with temperature?

0 Answers   Qualcomm,

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