Explain about stuck at fault models, scan design, BIST and IDDQ testing?

3 Answers   Intel,

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In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

0 Answers  

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What was your role in the silicon evaluation or product ramp? What tools did you use?

0 Answers   Intel,

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What are the Advantages and disadvantages of Mealy and Moore?

0 Answers   Intel,

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Explain various adders and difference between them?

0 Answers   Intel,

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Draw the SRAM Write Circuitry

0 Answers   Infosys,

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What are the various regions of operation of mosfet? How are those regions used?

0 Answers  

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Differences between Array and Booth Multipliers?

0 Answers   Intel,

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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

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Explain the working of differential sense amplifier?

1 Answers  

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Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)

6 Answers  

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What are the steps required to solve setup and hold violations in vlsi?

0 Answers  

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