Give the cross-sectional diagram of the cmos.
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Have you studied buses? What types?
Draw the SRAM Write Circuitry
What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?
Cross section of a PMOS transistor?
Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Explain various adders and difference between them?
Mention what are the different gates where Boolean logic are applicable?
Explain sizing of the inverter?
what is SCR (Silicon Controlled Rectifier)?
Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
What was your role in the silicon evaluation or product ramp? What tools did you use?