Why is OOPS called OOPS? (C++)

1 Answers   ARM, Intel,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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How can you construct both PMOS and NMOS on a single substrate?

0 Answers   IBM, Intel,

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What are the steps involved in preventing the metastability?

0 Answers  

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What is latchup? Explain the methods used to prevent it?

2 Answers   Intel,

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Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

0 Answers   Infosys,

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How to find the read failiure probablity in SRAM?

2 Answers  

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In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

0 Answers   Infosys,

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Explain what is scr (silicon controlled rectifier)?

0 Answers  

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What is FPGA?

7 Answers   Intel,

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What are the different design techniques required to create a layout for digital circuits?

0 Answers  

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Explain Custom Design Flow?

2 Answers   Intel,

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