Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

0 Answers   Infosys,

---

How does a pn junction works?

2 Answers   Wipro,

---

In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

0 Answers  

---

What are the main issues associated with multiprocessor caches and how might you solve them?

0 Answers   Intel,

---

Differences between blocking and Non-blocking statements in Verilog?

5 Answers   Intel,

---

How can you model a SRAM at RTL Level?

0 Answers   Infosys,

---

Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?

6 Answers   Intel,

---

Differences between DRAM and SRAM?

14 Answers   Infosys, Intel, University, Wipro,

---

Why do we use a Clock tree?

3 Answers   Intel,

---

Describe the various effects of scaling?

0 Answers   Infosys,

---

Draw a 6-T SRAM Cell and explain the Read and Write operations

0 Answers   Infosys,

---

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

0 Answers   Infosys,

---