What happens to delay if we include a resistance at the output of a CMOS circuit?

1 Answers   Infosys,

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If not into production, how far did you follow the design and why did not you see it into production?

1 Answers   Intel,

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What are the main issues associated with multiprocessor caches and how might you solve them?

1 Answers   Intel,

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Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

0 Answers   Infosys,

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Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?

0 Answers   Intel,

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Are you familiar with the term MESI?

1 Answers   Intel,

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what is a sequential circuit?

0 Answers  

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What happens if we increase the number of contacts or via from one metal layer to the next?

1 Answers   Infosys,

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Mention what are three regions of operation of mosfet and how are they used?

0 Answers  

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Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

13 Answers   Intel,

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In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

3 Answers   IBM, Intel, nvidia,

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For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?

2 Answers  

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