Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

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Differences between netlist of HSPICE and Spectre?

1 Answers   Intel,

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What is SPICE?

4 Answers   Intel,

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What is a D-latch? Write the VHDL Code for it?

3 Answers   Intel,

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What happens to delay if we include a resistance at the output of a CMOS circuit?

1 Answers   Infosys,

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What is the build-in potential?

1 Answers   Wipro,

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Working of a 2-stage OPAMP?

0 Answers   Intel, Tata Elxsi,

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Explain the various MOSFET Capacitances & their significance ?

1 Answers   Infosys,

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Explain why present VLSI circuits use MOSFETs instead of BJTs?

0 Answers  

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Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

0 Answers   Infosys,

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what is the doping?

5 Answers  

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what is Early effects and their physical origin.

1 Answers  

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