Explain about stuck at fault models, scan design, BIST and IDDQ testing?

3 Answers   Intel,

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what is the doping?

5 Answers  

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How does Resistance of the metal lines vary with increasing thickness and increasing length?

3 Answers   Infosys,

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How many bit combinations are there in a byte?

6 Answers   Intel,

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What are the different gates where boolean logic are applicable?

0 Answers  

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Draw the Layout of an Inverter?

0 Answers   Intel,

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In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

0 Answers   Infosys,

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What are the changes that are provided to meet design power targets?

0 Answers  

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Explain ASIC Design Flow?

2 Answers   Intel, JK Associates, Mind Tree,

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Explain the Charge Sharing problem while sampling data from a Bus?

1 Answers  

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Explain the usage of the shared SPI bus?

1 Answers  

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Draw a 6-T SRAM Cell and explain the Read and Write operations

0 Answers   Infosys,

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