Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

3 Answers   Intel,

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What does it mean “the channel is pinched off”?

0 Answers  

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Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

0 Answers   Infosys,

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.

0 Answers   Infosys,

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Draw a 6-T SRAM Cell and explain the Read and Write operations

0 Answers   Infosys,

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What types of high speed CMOS circuits have you designed?

0 Answers   Intel,

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Implement F = AB+C using CMOS gates?

2 Answers   Intel,

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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

0 Answers   Infosys,

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What are the total number of lines written by you in C/C++? What compiler was used?

1 Answers   Intel, Zensar,

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What does the above code synthesize to?

0 Answers   Intel,

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What are the various regions of operation of mosfet? How are those regions used?

0 Answers  

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What transistor level design tools are you proficient with? What types of designs were they used on?

0 Answers   Intel,

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