What is the difference between nmos and pmos technologies?

0 Answers  

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Why don?t we use just one NMOS or PMOS transistor as a transmission gate?

2 Answers   Infosys,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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Mention what are the different gates where Boolean logic are applicable?

0 Answers  

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Differences between IRSIM and SPICE?

0 Answers   Intel,

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Explain the various MOSFET Capacitances & their significance?

1 Answers  

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Explain about 6-T XOR gate?

0 Answers   Intel,

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How many bit combinations are there in a byte?

6 Answers   Intel,

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How do you detect a sequence of "1101" arriving serially from a signal line?

7 Answers   nvidia,

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What happens if we delay the enabling of Clock signal?

4 Answers  

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Explain the operation considering a two processor computer system with a cache for each processor.

0 Answers   Intel,

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Insights of a Tri-State Inverter?

3 Answers   Intel,

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