Explain sizing of the inverter?

0 Answers   Infosys,

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Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

0 Answers  

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What are the steps required to solve setup and hold violations in vlsi?

0 Answers  

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What is Noise Margin? Explain the procedure to determine Noise Margin?

4 Answers   Amkor, Cisco, Infosys, Intel,

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What is LVS, DRC?

10 Answers   IBM, Intel,

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Given a circuit and asked to tell the output voltages of that circuit?

1 Answers   Intel, Omega Healthcare,

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Mention what are the different gates where Boolean logic are applicable?

0 Answers  

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Insights of a 2 input NOR gate. Explain the working?

1 Answers   Infosys, Intel,

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Implement F = AB+C using CMOS gates?

2 Answers   Intel,

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Explain about 6-T XOR gate?

0 Answers   Intel,

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What is Body Effect?

0 Answers   CG CoreEL, Cisco, TA,

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Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

0 Answers   Intel, Sun Microsystems,

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