What is the difference between nmos and pmos technologies?
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For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?
Explain the difference between write through and write back cache.
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What are the steps involved in preventing the metastability?
Explain how MOSFET works?
what is multiplexer?
For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
what is short Channel effect.
What is validation?
What?s the critical path in a SRAM?
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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
What is the mealy and moore machine's state diagram that can detect 3 consecutive heads of 3 coins ?