Answer / rahul hiware

to implement user define malloc() function

Answer / guest

Matrix

Answer / omprakash

fibonacci series

Draw a 6-T SRAM Cell and explain the Read and Write operations

0 Answers   Infosys,

---

If the current thru the poly is 20nA and the contact can take a max current of 10nA how would u overcome the problem?

1 Answers   Intel,

---

Why is OOPS called OOPS? (C++)

1 Answers   ARM, Intel,

---

What is LVS, DRC?

10 Answers   IBM, Intel,

---

Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

---

---

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

---

Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

0 Answers   Infosys,

---

Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

---

What happens if we delay the enabling of Clock signal?

4 Answers  

---

In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

3 Answers   IBM, Intel, nvidia,

---

Draw the stick diagram of a NOR gate. Optimize it

0 Answers   Infosys,

---

What are set up time & hold time constraints? What do they signify?

3 Answers  

---