Implement a function with both ratioes and domino logic and merits and demerits of each logic?

0 Answers   Intel,

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Describe the various effects of scaling?

0 Answers   Infosys,

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What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

0 Answers   Infosys,

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Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;

0 Answers  

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What is pipelining and how can we increase throughput using pipelining?

1 Answers   Intel,

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Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to?

1 Answers   IIT, Intel,

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What does the above code synthesize to?

0 Answers   Intel,

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Given a circuit and asked to tell the output voltages of that circuit?

1 Answers   Intel, Omega Healthcare,

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What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

1 Answers   Intel,

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Explain what is Verilog?

0 Answers  

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Advantages and disadvantages of Mealy and Moore?

2 Answers   Intel,

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What is validation?

2 Answers   Intel,

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