What are the total number of lines written by you in C/C++? What compiler was used?

1 Answers   Intel, Zensar,

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How can you construct both PMOS and NMOS on a single substrate?

0 Answers   IBM, Intel,

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For CMOS logic, give the various techniques you know to minimize power consumption

0 Answers   Infosys,

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For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?

5 Answers   Intel,

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WHAT IS THE DIFFERENCE BETWEEN TESTING AND VERIFICATION OF VLSI CIRCUIT?

5 Answers   Intel, Wipro,

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Explain the usage of the shared SPI bus?

1 Answers  

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What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

0 Answers   Infosys,

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Insights of a pass gate. Explain the working?

0 Answers   Intel,

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What are set up time & hold time constraints? What do they signify?

3 Answers  

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For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

0 Answers   Intel,

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What are the different design constraints occur in the synthesis phase?

0 Answers  

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What products have you designed which have entered high volume production?

1 Answers   Intel,

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