Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
- 0 Answers
- 888 Views
- Infosys, I also Faced
- E-Mail Answers
No Answer is Posted For this Question
Be the First to Post Answer
what is the use of defpararm?
What are the different limitations in increasing the power supply to reduce delay?
Insights of a Tri-state inverter?
What was your role in the silicon evaluation/product ramp? What tools did you use?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
What is the difference between cmos and bipolar technologies?
Differences between DRAM and SRAM?
14 Answers Infosys, Intel, University, Wipro,
What are set up time & hold time constraints? What do they signify?
What is the ideal input and output resistance of a current source?
What are the different types of skews used in vlsi?
What is Fowler-Nordheim Tunneling?
what is the difference between the TTL chips and CMOS chips?
86 Family 
