Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
- 0 Answers
- 986 Views
- Infosys, I also Faced
- E-Mail Answers
No Answer is Posted For this Question
Be the First to Post Answer
What is validation?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
Design an 8 is to 3 encoder using 4 is to encoder?
How to find the read failiure probablity in SRAM?
What is clock feed through?
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
What are the two types of noise of MOSFET, how to eliminate them?(Thermal and Flicker).
Explain the operation considering a two processor computer system with a cache for each processor.
Explain about 6-T XOR gate?
Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?
If not into production, how far did you follow the design and why did not you see it into production?
Give the various techniques you know to minimize power consumption?
86 Family 
