Explain the concept of a Clock Divider Circuit? Write a VHDL
code for the same?
Answer Posted / senthil
I am using the Mr.Suriya code with little modification.
ENTITY CLK_DIV IS
PORT(CLK: IN STD_LOGIC;
NEWCLK:OUT STD_LOGIC);
END CLK_DIV
ARCH BEH OF CLK_DIV IS
VARIABLE COUNT:INTEGER:=0;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
COUNT:=COUNT+1;
IF COUNT=8000000 THEN
NEWCLK<= '1';
COUNT:=0;
ELSE
NEWCLK<= '0';
END IF;
END IF;
END PROCESS;
END BEH;
| Is This Answer Correct ? | 12 Yes | 12 No |
Post New Answer View All Answers
Explain how Verilog is different to normal programming language?
Explain what is multiplexer?
What are the different design techniques required to create a layout for digital circuits?
How to improve these parameters? (Cascode topology, use long channel transistors)
What transistor level design tools are you proficient with? What types of designs were they used on?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
Differences between IRSIM and SPICE?
What was your role in the silicon evaluation/product ramp? What tools did you use?
What are the steps involved in preventing the metastability?
What is the difference between cmos and bipolar technologies?
What is look up table in vlsi?
Explain various adders and difference between them?
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
What are the different classification of the timing control?
Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and diffusion layers etc?