What is look up table in vlsi?
Explain various adders and diff between them?
What is polymorphism? (C++)
what is the doping?
Describe the various effects of scaling?
What are the steps involved in designing an optimal pad ring?
What are the different design techniques required to create a layout for digital circuits?
Help with VHDL programming. Write a VHDL code for a D-Latch with clear input ?? (Hint: Set up a “Process” with appropriate sensitivity list to get the desired D-Latch with Clr working.) Inputs AND OUTPUTS: entity Lab4b is Port ( Clr, Clk, D : in STD_LOGIC; Q : out STD_LOGIC); end Lab4b;
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
Why is Extraction performed?
What is SPICE?
Write a pseudo code for sorting the numbers in an array?
Explain what is Verilog?