What types of high speed CMOS circuits have you designed?

0 Answers   Intel,

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How does Vbe and Ic change with temperature?

0 Answers   Qualcomm,

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What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

0 Answers   Infosys,

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Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

13 Answers   Intel,

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What happens to delay if we include a resistance at the output of a CMOS circuit?

1 Answers   Infosys,

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Explain how MOSFET works?

0 Answers  

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Explain Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

0 Answers   Intel,

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Write a VLSI program that implements a toll booth controller?

0 Answers   Patni,

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what are three regions of operation of MOSFET and how are they used?

0 Answers  

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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

0 Answers   Infosys,

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For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

0 Answers   Infosys,

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Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

0 Answers   Infosys,

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