verify nmos passes good logic 0 and passes bad logic 1.also verify that pmos passes good logic 1 and passes bad logic 0.

2 Answers   Cosmic Circuits, HP,

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In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

1 Answers   Intel,

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If not into production, how far did you follow the design and why did not you see it into production?

1 Answers   Intel,

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Insights of a Tri-State Inverter?

3 Answers   Intel,

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Give the various techniques you know to minimize power consumption?

5 Answers  

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Explain about 6-T XOR gate?

0 Answers   Intel,

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Explain sizing of the inverter?

0 Answers   Infosys,

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what is Channel length modulation?

2 Answers   Intel,

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What is the mealy and moore machine's state diagram that can detect 3 consecutive heads of 3 coins ?

2 Answers  

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What are set up time & hold time constraints? What do they signify?

3 Answers  

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Why do we use a Clock tree?

3 Answers   Intel,

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What are the steps involved in designing an optimal pad ring?

0 Answers  

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