Interested to Buy Any Domain ? << Click Here >> for more details...
Explain about stuck at fault models, scan design, BIST and
IDDQ testing?
- 3 Answers
- 13378 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / navya
IDDQ testing:usually performed at the beginning of test cycle.The test checks for leakage current to know if it is in normal range or abnormal range.If abnormal die fails,it is rejected and no further tests are performed.Iddq testing can detect clusters of gate oxide shorts(GOS) where gate voltage has no control over drain current and they tend to increase leakage levels.
BIST(built in self test): used to meet requirements such as high reliability and low repair cycle times.Bist reduces need for external testing(ATE).But the disadvantage is additional silicon area needed to implement BIST circuitry.
Scan design:test methodology built into digital chips
All flipflop are provided with alternate i/p for data as well as a separate clk i/p for scan testing.F/f connected together in scan chains.Testing is done by entering a special test mode called "scan mode" where test vectors is i/p to each scan chain and the bits clkd through all f/f's in the chain with resulting o/p chkd for errors.
Stuck at fault models:
stuck-on fault:always conducts Ids with an applied Vds,gate has no control over the operation
stuck off faults:current never flows regardless of Vgs or Vds.
| Is This Answer Correct ? | 13 Yes | 1 No |
Post New Answer View All Answers
Describe the various effects of scaling?
What are the steps required to solve setup and hold violations in vlsi?
Give various factors on which threshold voltage depends.
Draw a CMOS Inverter. Explain its transfer characteristics
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes with increasing Vgs.
Explain the Various steps in Synthesis?
Explain the working of Insights of an inverter ?
What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
What is the difference between nmos and pmos technologies?
what are three regions of operation of MOSFET and how are they used?
what is SCR (Silicon Controlled Rectifier)?
What are the different classification of the timing control?
Are you familiar with the term MESI?
