Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
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Give the various techniques you know to minimize power consumption?
Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?
what is the difference between the testing and verification?
Explain the working of Insights of a pass gate ?
Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
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What transistor level design tools are you proficient with? What types of designs were they used on?
For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the centre metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
What types of high speed CMOS circuits have you designed?
What types of CMOS memories have you designed? What were their size? Speed?
What is validation?
What are the different classification of the timing control?