In Verilog code what does “timescale 1 ns/ 1 ps” signifies?

0 Answers  

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What are the changes that are provided to meet design power targets?

0 Answers  

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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

0 Answers   Infosys,

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What are the limitations in increasing the power supply to reduce delay?

2 Answers   Infosys,

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Differences between DRAM and SRAM?

14 Answers   Infosys, Intel, University, Wipro,

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How does a Bandgap Voltage reference work?

0 Answers  

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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.

0 Answers   Infosys,

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Explain the Working of a 2-stage OPAMP?

0 Answers   Intel,

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What is the depletion region?

1 Answers  

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what is Latch up?How to avoid Latch up?

3 Answers  

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Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

4 Answers   Intel,

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What was your role in the silicon evaluation or product ramp? What tools did you use?

0 Answers   Intel,

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