Golgappa.net | Golgappa.org | BagIndia.net | BodyIndia.Com | CabIndia.net | CarsBikes.net | CarsBikes.org | CashIndia.net | ConsumerIndia.net | CookingIndia.net | DataIndia.net | DealIndia.net | EmailIndia.net | FirstTablet.com | FirstTourist.com | ForsaleIndia.net | IndiaBody.Com | IndiaCab.net | IndiaCash.net | IndiaModel.net | KidForum.net | OfficeIndia.net | PaysIndia.com | RestaurantIndia.net | RestaurantsIndia.net | SaleForum.net | SellForum.net | SoldIndia.com | StarIndia.net | TomatoCab.com | TomatoCabs.com | TownIndia.com
Interested to Buy Any Domain ? << Click Here >> for more details...

A circuit has 1 input X and 2 outputs A and B. If X = HIGH
for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B =
1. Draw a state diagram for this Spec?

Answer Posted / techie

PS X NS A B
S0 0 S1 0 0
S0 1 S2 0 0
S1 0 S3 0 0
S1 1 S2 0 0
S2 0 S1 0 0
S2 1 S4 0 0
S3 0 S5 0 0
S3 1 S2 0 0
S4 0 S1 0 0
S4 1 S6 0 0
S5 0 S0 0 1
S5 1 S2 0 0
S6 0 S1 0 0
S6 1 S0 1 0
This would be for non overlapping sequence. The above post correctly captrued overlapping sequence.

Is This Answer Correct ?    1 Yes 1 No



Post New Answer       View All Answers


Please Help Members By Posting Answers For Below Questions

What is the critical path in a SRAM?

3261


Basic Stuff related to Perl?

2869


Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

2381


Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

1354


what is multiplexer?

1227


For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?

1299


What are the Advantages and disadvantages of Mealy and Moore?

1348


Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.

3929


Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

1186


How does Vbe and Ic change with temperature?

3577


What happens if we use an Inverter instead of the Differential Sense Amplifier?

3059


What is the function of enhancement mode transistor?

1178


Write a VLSI program that implements a toll booth controller?

4026


what are three regions of operation of MOSFET and how are they used?

1301


What does it mean “the channel is pinched off”?

1406