Explain about stuck at fault models, scan design, BIST and IDDQ testing?

3 Answers   Intel,

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Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

0 Answers   Infosys,

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If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?

0 Answers   Intel,

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What is Noise Margin? Explain the procedure to determine Noise Margin?

0 Answers  

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What is threshold voltage?

0 Answers  

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Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?

3 Answers   Intel,

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Explain the various Capacitances associated with a transistor and which one of them is the most prominent?

2 Answers   Intel,

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How to improve these parameters? (Cascode topology, use long channel transistors)

0 Answers  

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What are the steps required to solve setup and hold violations in vlsi?

0 Answers  

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In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

3 Answers   IBM, Intel, nvidia,

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What is the mealy and moore machine's state diagram that can detect 3 consecutive heads of 3 coins ?

2 Answers  

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How do you detect if two 8-bit signals are same?

6 Answers  

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