Interested to Buy Any Domain ? << Click Here >> for more details...
A circuit has 1 input X and 2 outputs A and B. If X = HIGH
for 4 clock ticks, A = 1. If X = LOW for 4 clock ticks, B =
1. Draw a state diagram for this Spec?
- 3 Answers
- 9708 Views
- Intel, I also Faced
- E-Mail Answers
Answer Posted / user
PS X NS A B
S0 0 S1 0 0
S0 1 S2 0 0
S1 0 S3 0 0
S1 1 S2 0 0
S2 0 S1 0 0
S2 1 S4 0 0
S3 0 S5 0 0
S3 1 S2 0 0
S4 0 S1 0 0
S4 1 S6 0 0
S5 0 S5 0 1
S5 1 S2 0 0
S6 0 S1 0 0
S6 1 S6 1 0
| Is This Answer Correct ? | 5 Yes | 1 No |
Post New Answer View All Answers
what is the difference between the TTL chips and CMOS chips?
How can you model a SRAM at RTL Level?
What was your role in the silicon evaluation or product ramp? What tools did you use?
Explain the working of 4-bit Up/down Counter?
Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
What is the function of enhancement mode transistor?
What is Noise Margin? Explain the procedure to determine Noise Margin?
Calculate rise delay of a 3-input NAND gate driving a 3-input NOR gate through a 6mm long and 0.45m wide metal wire with sheet resistance R = 0.065 / and Cpermicron= 0.25 fF/m. The resistance and capacitance of the unit NMOS are 6.5k and 2.5fF. Use a 3 segment -model for the wire. Consider PMOS and NMOS size of reference inverter as 2 and 1 respectively. Use appropriate sizing for the NAND and NOR gate.
What does the above code synthesize to?
What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
What happens if we use an Inverter instead of the Differential Sense Amplifier?
Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes considering Channel Length Modulation.
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
Explain sizing of the inverter?
Explain the Charge Sharing problem while sampling data from a Bus?
